Partial Reconfiguration Fpga Thesis

Partial Reconfiguration Fpga Thesis-56
Then, weestablished connection between the peripherals and the processing system through an AXI DMA IP in Scatter/Gather mode.Scatter/Gather resulted in a high-speed communication and applied interruptcoalescing strategy to reduce the number of interrupts occupying the ARM, thus it allowed theprocessor to handle the peripherals more efficiently.

Then, weestablished connection between the peripherals and the processing system through an AXI DMA IP in Scatter/Gather mode.

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This thesis tried to explore the PR technology on FPGAs and apply theknowledge acquired to implement a cryptographic system on a Xilinx Zynq-7000 So C device.

Zynqcombines the coexistence of programmable logic and an embedded ARM processor on a single chip,thus forming a system-on-a-chip (So C), while enabling fast interconnection between them and powerefficiency.

While partial reconfiguration can offer many benefits, it is still rarely exploited in practical applications.

Few full realizations of partially reconfigurable systems in current FPGA technologies have been published.

Bus-based interconnect achieves better performance and consume less area and power than No Cbased scheme for the fully-connected feed-forward NN system.

This suggests buses are a better choice for systems that do not require many simultaneous communications or systems with broadcast communications like a fully-connected feed-forward NN.However, this brings drawbacks including resource utilization inefficiency, power consumption overhead and decrease in system operating frequency.The experimental results report a 50% of resource utilization inefficiency with a power consumption overhead of less than 5% and a decrease in frequency of up to 32% compared to a static implementation.Results from the experiments with dynamic partial reconfiguration demonstrate that buses have the advantages of better resource utilization and smaller reconfiguration time and memory than No Cs. They have the advantage of placing almost all of the communication infrastructure in the dynamic reconfiguration region.This means that different applications running on the FPGA can use different interconnection strategies without the overhead of fixed bus resources in the static region.We also applied decoupling strategy to isolate thereconfigurable modules during PR to avoid undesirable outcoming signals to affect the rest of thedesign.Finally, we made an evaluation of our work and constructed a benchmark to show theacceleration advantages of PR.For the purposes of this thesis we chose four cryptographic modules (AES128, AES192, AES256 and SHA3-512).Firstly, we made all the appropriate modifications needed to utilize thecryptographic modules in the So C and designed the appropriate AXI4-Stream compliant interfaces toenable communication between the peripherals and the processor, with respective compromises to thedifferent modules’ architecture, the processing system’s limitations and PR’s restrictions.Field Programmable Gate Arrays (FPGAs)have gained the interest of system architects due to their rapid prototyping and fast acceleratordeveloping capabilities.As their name denotes, FPGAs are programmable "in the field", meaning thattheir internal logic can be configured after the fabrication process and modified, if needed, withoutgoing to re-fabrication process, as common ASICs.

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